Direct Design of Reversible Combinational and Sequential Circuits Using PSDRM Expressions

Reversible logic will be a favourable logic by dissipating less heat than the thermo dynamic limit for the emerging computing technologies. Also it has become very promising for low power designs. Reversible designs of Combinational and Sequential circuits are built by replacing the latches, flip-flops and associated combinational gates of the traditional irreversible designs by their reversible counter parts. But this replacement technique is not very promising because it leads to high quantum cost and garbage outputs. So, in this paper we presented both the direct design and replacement designs of 5-bit up down counter and universal shift register which are practically important using reversible logic and PSDRM expressions. Replacement design is done by replacing the RTL design using reversible designs. Direct design is done by representing the state transitions and the output functions of the circuits using PSDRM expressions which are obtained from truth table or state transition table. Thus my direct design of a 5-bit updown counter and universal shift register save 42.66%, 9.79% quantum cost and 93.75%, 40% garbage outputs respectively than the replacement design.